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Altera_Forum
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14 years ago

How to Implement VHDL Drawing Buffer in DE2

I'm having trouble making a drawing buffer in VHDL on the DE2.

I'm currently shooting for 640x480x8x3 bit resolution.

In my current implementation I am bit-banging the VGA protocol in a 2-3-3 RGB @ 50 MHZ. So at each clock I perform a half (1/2 + 1/2 in 25 MHZ) of the read operation for each pixel. The pixel is then expanded from the 2-3-3 format into the 8-8-8 RGB output signal.

At this rate I can only read (not write) and the colors are ugly. I cannot write because my memory's data signal is must constantly be fetching data to display. I saw some projects (For example zet.aluzina.org/index.php/zet_processor) using the same FPGA as me and they seem to have nice colors. Also they can write to the buffer, I can only read.

The only solutions I can think of to the read-write problems are:

-> use the VGA padding times to write 10% of the time and read 90% read time

-> Group pixels into 2x1 blocks and have 50% writing and 50% reading

I can't think of any solutions to the color problem except for making either of the two meathods four times slower.

How do the pros solve these problems? Is there any way to avoid these issues? How did computers in 1993 display VGA at similar resolutions?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    can't you use a processor such as NIOSII with (important) a bridged access to memory ?

    if the display takes half of the bandwidth, then the update must be lower than half in practice.

    It depends if you want to refresh the whole image every time, with a processor, you can simply update the pixels to change.

    If the whole image needs to be updated, then you just need to arbiter the access and to buffer a streaming update of the memory for example. you have to design it lower than the theoretical bandwidth (memory bank switching overhead), use bursting necessarily.

    Yes, that sounds like a complicated task for HDL only initiative, maybe SOPC-QSys could be a way out.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm not quite sure how the processor will get me past the lack of write cycles in the display operation unless it uses the "porch" time to write to the display.

    The trouble I am having is that I need to supply a signal at 25 MHZ (640x480x3x8), but with a system clock at 50 MHZ I can only supply (640x480x1x8 2 clks per memory access time). And doing this will leave me no time to write to memory (except for 10% porch time)!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You can use pipeline or burst transfers to read 32 bits per clock cycle. Then put a FIFO between your memory reader and the VGA output, so that you can use some cycles to write to the memory without interrupting the output flow.