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Honored Contributor
Honored ContributorHow to Implement VHDL Drawing Buffer in DE2
I'm having trouble making a drawing buffer in VHDL on the DE2. I'm currently shooting for 640x480x8x3 bit resolution. In my current implementation I am bit-banging the VGA protocol in a 2...
Altera_ForumHonored Contributor
Honored ContributorYou can use pipeline or burst transfers to read 32 bits per clock cycle. Then put a FIFO between your memory reader and the VGA output, so that you can use some cycles to write to the memory without interrupting the output flow.
