How to implement a 32K lookup table in CPLD?

hello,

I'm newbie in VHDL, FPGAs and CPLDs devices. I would like some help for implement a lookup table with 2048 words (2 bytes).

The table should be: 2048x16bits (32K), I mean, 11 bits address (A10-A0) and 16 bits data (D15-D0). As soon as the address is placed on the bus, the fastest possible data should appear (no latch or enable is used).

Please, could somebody guide in the implementation? Can I use a CPLD (EPM240 o EPM570)?

I need to use the fewest possible components, so I prefer a CPLD.

This the code I plan to use, but i think it will be very slow due to sequential process (assume that the latest addresses are used):

-----------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY lookuptable IS

PORT (address : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

) ;

END lookuptable ;

ARCHITECTURE behavior OF lookuptable IS

BEGIN

PROCESS ( address )

BEGIN

CASE address IS

WHEN "00000000000" => data <= "1111111111111111"; -- example data, all "1s"

WHEN "00000000001" => data <= "1111111111111111"; -- example data, all "1s"

WHEN "00000000010" => data <= "1111111111111111"; -- example data, all "1s"

WHEN "00000000011" => data <= "1111111111111111"; -- example data, all "1s"

.

.

.

WHEN "11111111101" => data <= "1111111111111111"; -- example data, all "1s"

WHEN "11111111110" => data <= "1111111111111111"; -- example data, all "1s"

WHEN "11111111111" => data <= "1111111111111111"; -- example data, all "1s"

WHEN OTHERS => data <= "0000000000000000"; -- example data, all "0s"

END CASE;

END PROCESS;

END behavior

-----------------------------------------------------------------------

I know that altsyncram (with ROM, single-port) Megafunction option exist , but this will force to use a FPGA device (more expensive and need more electronics components around it). That is my last option.

Thank you !