Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

how to generate clocks manually in FPGA?

Hi

I am programming a module in verilog that use serial input.

Because I am using serial input I need a slow clock that i can test my circuit on FPGA device.

i heard from on of my friends that if I map fpga push button to my clock input i can make clocks manually every time that i want with push the button and i never will need to work with 27 MHz clock.

i want to now is this assumption true or i should search for some other ways?

thank you very much.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You can use a counter to generate a slow clock, then drive it through a global buffer to your logic. Basically you use a fast clock, count to some high value (determined by your fast frequency and intended frequency), then toggle a slow clock reg and clear the counter.

    You could also use one of the PLLs, or more in cascade.

    There's tons of examples online for either method.

    I would say your push button method would not be a good method, because you will need to debounce it anyways (usually with a counter)

    Edit:Whatever you do don't use a ripple counter as a clock - too much skew
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    When you are bringing asynchronous signals into your design from outside a FPGA, be sure to register the value at least once.

    I would suggest registering the input with a clock at least 4x faster than your maximum symbol rate if possible. This should ensure you will find every bit.

    I would also suggest using clock enables instead of clock dividers. Using these should make the timing behavior easy to work with (so you don't need to worry about crossing clock domains).