how to generate clocks manually in FPGA?

When you are bringing asynchronous signals into your design from outside a FPGA, be sure to register the value at least once.

I would suggest registering the input with a clock at least 4x faster than your maximum symbol rate if possible. This should ensure you will find every bit.

I would also suggest using clock enables instead of clock dividers. Using these should make the timing behavior easy to work with (so you don't need to worry about crossing clock domains).