how to generate clocks manually in FPGA?

You can use a counter to generate a slow clock, then drive it through a global buffer to your logic. Basically you use a fast clock, count to some high value (determined by your fast frequency and intended frequency), then toggle a slow clock reg and clear the counter.

You could also use one of the PLLs, or more in cascade.

There's tons of examples online for either method.

I would say your push button method would not be a good method, because you will need to debounce it anyways (usually with a counter)

Edit:Whatever you do don't use a ripple counter as a clock - too much skew