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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to generate a clock signal using combinational logic

For some reasons, my board doesn't feed a clock to the cpld, and i need a clock signal for some functions, so i want to using combinational logic to generate a clock signal. Can anyone give me some advices?!

BTW, i just need a rough clk signal, not accurate, such toggling signal is ok!!!

Thanks a lot!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Ok， I got it！ It's very usefule for me！

    Thank you very much！
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you're targeting to classical Altera CPLD as MAX3000 or MAX7000, you'll realize, that the synthesis attributes needed to keep logic cells for a ring oscillator most likely won't work, because they are apparently unsupported by the CPLD synthesis tools. They can work with MAX II, that uses FPGA synthesis tools.