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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to force de2-115 to work at 100mbps Ethernet

Hi,

We are trying to implement an Ethernet MAC sublayer of our own, according to the IEEE standard.

We don't want to implement the whole standard, but only the portion that relates to 100Mbps with the MII.

We are using the developing and education board DE2-115

(Can we achieve our goal with this board?)

We tried but with no success to force the PHY to work at 100Mbs although it connected in the other side to a 1Gbs PHY.

Which values we need to send to our PHY and by which signals?

We need to do it by tied ENET0_GTX_CLK to GND?

We tried to do so while we are resetting the PHY by the RESETn signal, it didn't made any change.

Thanks for your help

Eddie

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You basically have two ways:[list][*]The easy way: connect a 100MBps switch between your kit and its target

    [*]The slightly harder way: write 0 to MDIO register 9 to disable gigabit capability advertising, and then set bit 9 of MDIO register 0 to 1 to trigger a new auto-negotiation. Both ends should then negotiate a 100Mbps link.[/list]

    And please post your question only once.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    First, thanks for the quick replay,

    and to know that someone has info about it cause I didn't find anything about that at the net, any manual or instractions.

    Second, I'm so newbie on the FPGA and verilog field, are you familier with any reference that can assist with how to do the second option that you offered.

    as I understand the the MDIO is a one bit signal, how can I write just to it's 9th register?

    Thanks again for your help, and sorry about posting twice the question that made by mistake

    Eddie
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This kind of information isn't available publicly, as Marvell seems to think that information about how to use their PHY is an industry secret and they keep it under an NDA. Marvell components should be avoided on development kits for this reason alone...

    MDIO is a standard bus to access Ethernet PHY registers, you should be able to find lots of documentation about it on the net. Unfortunately only the registers to control the 10/100 MBps operations are standardized, and those for gigabit control are vendor specific.

    You need two signals for the MDIO bus, one is the clock (MDC) and the other one is a bidirectionnal data signal (MDIO). If you use the Triple Speed Ethernet core in the FPGA there is an integrated MDIO controller that you can use (check the tse documentation (http://www.altera.com/literature/ug/ug_ethernet.pdf)) and if you aren't there is a MDIO core available (check chapter 14 of the embedded ip documentation (http://www.altera.com/literature/ug/ug_embedded_ip.pdf)).