Honored Contributor
Honored ContributorThis kind of information isn't available publicly, as Marvell seems to think that information about how to use their PHY is an industry secret and they keep it under an NDA. Marvell components should be avoided on development kits for this reason alone...
MDIO is a standard bus to access Ethernet PHY registers, you should be able to find lots of documentation about it on the net. Unfortunately only the registers to control the 10/100 MBps operations are standardized, and those for gigabit control are vendor specific. You need two signals for the MDIO bus, one is the clock (MDC) and the other one is a bidirectionnal data signal (MDIO). If you use the Triple Speed Ethernet core in the FPGA there is an integrated MDIO controller that you can use (check the tse documentation (http://www.altera.com/literature/ug/ug_ethernet.pdf)) and if you aren't there is a MDIO core available (check chapter 14 of the embedded ip documentation (http://www.altera.com/literature/ug/ug_embedded_ip.pdf)).
