Forum Discussion
The design is fully constrained and the clock is defined per the sdc. The design also has thousands of other nets that the tool associates with a clock domain, and it is using my I/O and default toggle rates (percentages I input into the tool) without any problem on those thousands of other nets.
I am trying to find out why in particular it cannot associate a clock domain automatically with those 18 nets after it infers the multiplier from my VHDL. This is a deep dive question as to why those 18 nets are behaving differently from the thousands of other nets in the design where the power analysis tool finds the clock domain without any issue. I know that it is the 18 nets of the multiplier because in the power analysis report, they are listed under "indeterminate toggle rates."
Even if my default toggle rates cause the tool to give a low confidence rating versus a vcd, I should still be able to get an answer to this question from someone in the factory who understands why the multiplier IP in the Max 10 is causing the power analysis tool to treat the registered multiply as if it is unregistered?