New ContributorHow to fit 2 multipliers in one DSP block - Cyclone V GX
Hi all,
I am optimizing a filter that was made in a Cyclone V device. The current filter uses two DSP blocks
for two multiplications; according to the Cyclone V device handbook, it should be possible to fit two
independent multipliers in one DSP block. I tried to implement the multipliers by using the ‘Multiply
adder’ intel FPGA which uses the ‘altera_mult_add’ module from the ‘altera_lm’ library.
Unfortunately, it seems to implement the two multipliers in ‘Multiplier Adder mode’, this mode is
shown in the figure below.
I would like to implement the two multipliers independently. However, I can’t figure out how I can bypass the adder from the DSP block as shown in the next figure.
I would be very thankful if someone can give me a solution to this problem, I am working with the
Intel FPGA lite 18.1 software.
Kind regards,
Bas van Wijngaarden
Hi all,
I was working with SanderWeijers on the same project and we had given up this issue at some point.
Last week I decided to have one last attempt into solving this problem which - if solved - could lead into an enormous resource improvement regarding DSP block usage. We finally found the solution and I will place it here for future reference, afterwards we also saw that this solution was brought up in the following thread: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Instantiation-of-9x9-multipliers-in-cyclone-V-GT-FPGA/m-p/701753/highlight/true?profile.language=en.
We have to use the Logic Lock (LL) regions feature which is not available in Quartus Prime Lite, therefore we can use Quartus Prime Standard to improve the DSP block usage in the example project. The logic lock regions force the fitter to place two independent multipliers into one DSP block. I will describe a step by step approach to solve the problem in the example project since it is a little bit complicated.
1) First we download the .qar file given by Sander on 06-29-2023
2) Synthesize the project, we see that the DSP block usage will be 15 DSP blocks. If we would run the fitter now, the DSP block
usage would stay at 15. You might expect a DSP block usage of 16 blocks, but the first DSP block is in 'sum of two 18x18' mode which makes it possible for the fitter to directly place the two multipliers into one block together with the adder functionality. Our issue is with the other 7 dual_multipliers which are in 'two independent 18x18' mode and now utilize 14 DSP blocks.
3) Open the chip planner: Tools -> Chip Planner
4) Find the DSP blocks in the chip planner
5) Go to: View -> Logic Lock Regions -> Create Logic Logic region, and create a region that fits exactly the amount of blocks we have to fit; in this case we have to create a region which consists of 7 DSP blocks only!
6) Right click on the region and go to: Logic Lock Regions -> Logic Lock Region Properties
7) Click on add and in the 'Add Node' window under 'Node Name ' add 'dual_multiplier:\multipliers:1:multiplier:i_dual_multiplier', also do this for multipliers 2 to 7. Do not add multiplier 0 since this is the MULT_ADD .Now you have added the 7 'dual_multipliers' in the 'Add Node' window we have to make sure that only DSP blocks are fitted into the LL regions. To do this click on 'edit' under 'excluded element types' in the 'add node' window. Now exclude everything but the DSP block. In this way, the fitter is only forced to put the multipliers into the DSP block, but the logic does not have to be there.
9) Click three times on the 'ok' button.
10) Run the fitter
11) You will find that the total DSP blocks now are reduced to only 8.
The picture below is used to clarify some point of the step-by-step approach here above.
The highlighted dark blue lines depict the LL region which consists of the 7 DSP blocks (which I gave a light blue color). In the Logic Lock properties you see the design elements that I added and also the excluded element types which gives the fitter more freedom.If we now look into the Technology map viewer we see that the fitter successfully uses the two multipliers from each DSP block and also bypasses the adder.
