Hi all! I'm using Quartus TQ and I have a question about the best way to measure a Tco for a FPGA pin to pin. My task is specifically for the case in that example - https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp_stxtco.pdf. In Figure 2. Sample tCO Design we see 3 FFs, so commands like report_path and report_timing as I figured out can't give result immediately - I need to iteratively use them for FF-to-FF path for example. Is it another option, for example to view the summary of paths from input to output pin using one command? Thanks in advance.

This is a really old white paper based off of the old timing analyzer. Are you trying to meet timing through a device or are you talking about meeting I/O timing to/from external devices? You should have set_input_delay and set_output_delay constraints in your .sdc file defining the external timing delays to/from external devices. You can then use (based on the paper you linked): report_timing -from [get_ports din*] -to [get_ports dout*] to generate timing reports on these paths.

Thank you for your answer, sstrell! I agree, it is an old white paper and I realized it is a classic timing analyzer which is used there. The task is how to meet timing through a device, I mean how to calculate or view total propagation time from input pin to output pin of FPGA, like in old white paper mentioned. For I/O timing from external device of course I have to use set_input_delay and set_output_delay constraints. I tried to follow your suggestion ("report_timing -from [get_ports din*] -to [get_ports dout*] to generate timing reports on these paths") I added such constraints in sdc file: # ************************************************************** # Set Input Delay # ************************************************************** set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din1] set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din1] set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din2] set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din2] set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din3] set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din3] set_input_delay -clock CLK_EXT_input_side -max 0.0 [get_ports din4] set_input_delay -clock CLK_EXT_input_side -min 0.0 [get_ports din4] # ************************************************************** # Set Output Delay # ************************************************************** set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout1] set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout1] set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout2] set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout2] set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout3] set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout3] set_output_delay -clock CLK_EXT_output_side -max 0.0 [get_ports dout4] set_output_delay -clock CLK_EXT_output_side -min 0.0 [get_ports dout4] and also write a report_timing command: report_timing -from [get_ports {din1}] -to [get_ports {dout1}] -npaths 10 -detail full_path -panel_name {Report Timing} -multi_corner and even just report_timing -from [get_ports {din1}] -to [get_ports {dout1}] But I received such answer: Report Timing: No setup paths were found. So maybe I misunderstood your advice, but it didn't work for me now.

You can't use a min and max of 0 for set_input/output_delay. And I presume you've already constrained the clocks as well.

I thought that I can use a min and max of 0 for set_input/output_delay, it just means that I give information about virtual clock and describe outside-of-FPGA clocking scheme, example of that can be seen on page 15-16 of rysc's TimeQuest User Guide (http://www.alteraforum.com/alterawiki.com/uploads/3/3f/timequest_user_guide.pdf). Here is my whole sdc file (I changed -max and -min from 0 to 1 just for test, it changes nothing, still reported "No setup paths were found.") : # ************************************************************** # Create Clock # ************************************************************** create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK}] create_clock -name {CLK_EXT_output_side} -period 5.000 -waveform { 0.000 2.500 } create_clock -name {CLK_EXT_input_side} -period 5.000 -waveform { 0.000 2.500 } # ************************************************************** # Create Generated Clock # ************************************************************** derive_pll_clocks # ************************************************************** # Set Input Delay # ************************************************************** set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din1] set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din1] set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din2] set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din2] set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din3] set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din3] set_input_delay -clock CLK_EXT_input_side -max 1.0 [get_ports din4] set_input_delay -clock CLK_EXT_input_side -min 1.0 [get_ports din4] # ************************************************************** # Set Output Delay # ************************************************************** set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout1] set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout1] set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout2] set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout2] set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout3] set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout3] set_output_delay -clock CLK_EXT_output_side -max 1.0 [get_ports dout4] set_output_delay -clock CLK_EXT_output_side -min 1.0 [get_ports dout4]

Hi, sstrell! Maybe some other thoughts, do you agree with my opinion?

How to find out a Tco from TimeQuest | Altera Community

14 Replies

Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Hi kaz!

Yes, exactly, as about tCO parameter it is what you wrote. I was interested if there is such parameter that sum tCO and integrated clock cycles on other register (a path from input pin to output pin with intermediate registers inside the path).
--- Quote End ---

data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.
Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)

so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.
Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)

so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period
--- Quote End ---

Yes, kaz, I absolutely agree with you! I just thought that there is a command to find out that value automatically without manual calculation.

Thank you very much!
Altera_Forum
Honored Contributor
8 years ago
That would be useful indeed for delay measurements. I used signaltap at some point just to measure delays.
For mobile Tx/Rx systems all delay figures are important and have to be worked out by various engineers part of which is FPGA.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
That would be useful indeed for delay measurements. I used signaltap at some point just to measure delays.
For mobile Tx/Rx systems all delay figures are important and have to be worked out by various engineers part of which is FPGA.
--- Quote End ---

Yes, kaz! So I think it would be great if such a total delay command would be inserted in TQ.

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How to find out a Tco from TimeQuest

14 Replies

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