How to estimate the effective bandwidth of cycloneiv ddr2 HPC II?

Hi

The project is almost complete. We are using 32bit DDR2 and set the DRR2 HCPII as 160Mhz DDR2 clock output. The input stream is 24bit x 148Mhz and same bandwidth as output stream.

So these is 8 bits watse on DDR2 side. Then we covert the 24bit RGB to YUV422 as simple compression. We use a 16bit to 32 bits FIFO as cross clock domian FIFO to make the best of DRR2's 32bits. Then it works.

Is these any solution can make the best of DRR2' s 32bits with 24bits RGB raw input?