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On FPGA2, have the PLL generate a clock with a 90º phase shift and use that to latch the data.
You'll notice your setup slacks will decrease and your hold slacks will increase.
PS: Somehow I forgot but when using DDR, you should set I/O constrains for both edges of the clock. This is done by repeating the constraint with -clock_fall -add_delay
set_input_delay -max XX -clock clk [get_ports fp1_co]
set_input_delay -max XX -clock clk -clock_fall [get_ports fp1_co] -add_delay
Same thing for min output delay and input delays.
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I see.Thanks.
And I encountered one case.However I adjusted the value of the tH,not all FPGAs could meet the timing.either FPGA1 or FPGA2 couldn't.
Does it mean that the timing cann't be met only through the timing constraint,and the desigh is needed to modify?For example,using a PLL to shift the phase
of the output clock.Right?
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