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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to do the timing constraint?

Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

On FPGA2, have the PLL generate a clock with a 90º phase shift and use that to latch the data.

You'll notice your setup slacks will decrease and your hold slacks will increase.

PS: Somehow I forgot but when using DDR, you should set I/O constrains for both edges of the clock. This is done by repeating the constraint with -clock_fall -add_delay

set_input_delay -max XX -clock clk [get_ports fp1_co]

set_input_delay -max XX -clock clk -clock_fall [get_ports fp1_co] -add_delay

Same thing for min output delay and input delays.