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Honored Contributor
Honored ContributorHow to do the timing constraint?
Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- What effect were you hoping for? As far as I can see, all the signals there have good setup/hold margins and you should not be getting any violations in post-fit simulation. --- Quote End --- The timing was OK,But the clock dindn't capture the data at the middle position of the data. And I hope it does.Do you have any way to do that?
