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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to do the timing constraint?

Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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What effect were you hoping for?

As far as I can see, all the signals there have good setup/hold margins and you should not be getting any violations in post-fit simulation.

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The timing was OK,But the clock dindn't capture the data at the middle position of the data.

And I hope it does.Do you have any way to do that?