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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to do the timing constraint?

Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The detail of the test mentioned above.

FPGA1 : registers to Outputs(Setup)

https://www.alteraforum.com/forum/attachment.php?attachmentid=6642

FPGA1 : registers to Outputs(Hold)

https://www.alteraforum.com/forum/attachment.php?attachmentid=6643

FPGA2 : Inputs to registers(Setup)

https://www.alteraforum.com/forum/attachment.php?attachmentid=6644

FPGA2 : Inputs to registers(Hold)

https://www.alteraforum.com/forum/attachment.php?attachmentid=6645

post-sim with connecting the both FPGA in series

https://www.alteraforum.com/forum/attachment.php?attachmentid=6647

the test's timing didn't reach the best effect.

At this case,the slack of setup had 5ns to 7ns.Wasn't it enough?

How to judge whether the timing has reached the best effect by the slack value?