How to do the timing constraint?

Thank you for your reply.

And I did the following test.

for example,

set fp2_tsu 7.8125

set fp2_th 0.0000

set fp1_max_tco [expr 15.625 - $fp2_tsu]

set fp1_min_tco [expr $fp2_th]

FPGA1:

set_output_delay -clock fp1_co -max [expr $fp2_tsu] [get_ports fp1_do[*]] -add_delay

set_output_delay -clock fp1_co -min [expr -$fp2_th] [get_ports fp1_do[*]] -add_delay

set_output_delay -clock fp1_co -max [expr $fp2_tsu] -clock_fall [get_ports fp1_do[*]] -add_delay

set_output_delay -clock fp1_co -min [expr -$fp2_th] -clock_fall [get_ports fp1_do[*]] -add_delay

FPGA2:

set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] [get_ports {fp2_di[*]}] -add_delay

set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] [get_ports {fp2_di[*]}] -add_delay

set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay

set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay

By TQ,the slack of setup timing is about 6ns to 7ns on both FPGA,but the slack of holdup timing is only about 0.5ns on both FPGA.

For this case,Need I adjust the value of fp2_th to increase the slack of holdup timing?