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Altera_Forum
Honored Contributor
Honored ContributorHow to do the timing constraint?
Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_ForumHonored Contributor
Honored ContributorThat's a labour intensive and/or error prone process.
Every time you run a new fit for FPGA1, you need to re-check the tCOs you got. If they're different from the tCOs you've constrained FPGA2 with, then you need to manually check and, if needed, update FPGA2's constrains and run a new fit If instead you specify reasonable constraints for both FPGAs that meet the conditions I wrote before, then you can just trust TQ to fail your design if something goes wrong. And if those constrains are well balanced between the FPGAs, you'll probably never have to change them again.
