How to do the timing constraint?

That's a labour intensive and/or error prone process.

Every time you run a new fit for FPGA1, you need to re-check the tCOs you got. If they're different from the tCOs you've constrained FPGA2 with, then you need to manually check and, if needed, update FPGA2's constrains and run a new fit

If instead you specify reasonable constraints for both FPGAs that meet the conditions I wrote before, then you can just trust TQ to fail your design if something goes wrong.

And if those constrains are well balanced between the FPGAs, you'll probably never have to change them again.