How to do the timing constraint?

If you set a max output delay of zero (external tSU of zero), you're not asking the tool to generate a tCO of zero, nor a tCO of 1 clock period.You're telling the tool any tCO below 1 clock period is good and the tool will try to achieve that, with minimum effort.In your example, the minimum effort solution for your design has a tCO of 15 ps, which meets the requirement by a mile.But, if by some fluke, the minimum effort solution had a tCO of 3 ns or 10 ns, then that's what you'd get. It still meets the requirement and you'd still get a pass from TimeQuest.Which is not good, since for the other FPGA, you're telling the tool the max tCO is has to deal with is 2 ns.(can't format my post now...)