How to do the timing constraint?

More generally, the rule would be

fp1_max_output_delay + fp2_max_input_delay >= clock period

fp1_min_input_delay + fp2_min_input_delay <= 0

But using equality gives you the most slack.

So, kaz suggestion meets this requirement for the min delays but not for the max.

Regarding max delays, kaz suggested to tell FPGA1 that tSU is zero and then to tell FPGA2 max tCO is 2 ns.

But, in fact, by telling FPGA1 that tSU is zero, the fitter may produce a design with a tCO of up to 1 clock period.

Vice versa, by telling FPGA2 that max tCO is 2, the fitter may produce a design which has a tSU of clock period - 2 ns.

It will be an iterative process. I'd start with zero for fp2_tH and half clock period for fp2_tSU and see what I get.

(something broked with post editing...)