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Using DDR and PLL may not be required in your case but you can keep your design as such then I will do the following:
The fpga1 can send data and clk aligned readily and all you need is set max and min output delay to zero implying there is no tSU/tH requirement so the fitter maintains the data clock alignment.
At fpga2 assume min tCO = -2ns & max tCO = +2ns then set max input delay to about +2ns and min delay to -2ns then the fitter will try avoid the edge area and hopefully centre data away from clock edges. Only if it fails then you can use PLL here.
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Thank you for your reply.And It seems that your timing constraint doesn't satisfy the following relationship mentioned by rbugalho.
fp1_max_output_delay + fp2_max_input_delay = clock period
fp1_min_output_delay + fp2_min_input_delay = 0
So you have diffrent thought about that?
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