How to do the timing constraint?

caobaiyu,

1. Trying to manually adjust delays by adding modules to your design is, generally, a bad idea for bunch of reasons: tools tend to optimize those things away or change the way they're placed. And of course, you have process/voltage/temperature variations.

The best way is simply to correctly constrain your design and let the tools do their job.

2. There's a (fairly big) delay between the clock delivered to the FPGA pin and the clock delivered to the flip-flops inside the FPGA, caused by the FPGA clock distribution tree. The PLL can compensate this delay by using the clock delayed by the clock tree as feedback clock. This will cause the clock delivered to the flip-flops to be phase aligned with the clock at the FPGA input pin.

Input/Output delays tell the tools about the delays/requirements of the system that surrounds the FPGA.

3: set_output_delay -min xx -clock clk [get_ports fp1_do] tells the tools that, after leaving the FPGA1 pins, fp1_do will be delayed by a minimum of xx ns and then be captured at the rising edge of clk

4: set_output_delay -max XX -clock clk [get_ports fp1_do] does an equivalent thing

Put in another way, it's telling the tools that fp1_do is going to flip-flops which operate on the rising edge of clk and have a tSU of XX ns and a tH of -xx ns.

5,6: set_input_delay -min yy -clock clk [get_ports fp2_di] tells the tools that fp1_di will have a minimum delay of yy ns. Equivalent thing for max.

Again, put in another way, it's telling the tools that fp2_di is produced by flip-flops operating on the rising edge of clk and have min_tCO of yy ns and max tCO of YY ns.

In case of doubt, draw a timing diagram.

The tools will then take this information into account and try to optimize the design inside the FPGAs to make sure that all timing requirements are respected.

7. If your constrains meet the relationship I wrote above and TimeQuest says timing requirements are met, then it's OK.

You can then try to look at the I/O timings slack in both FPGAs. If one FPGA has large slacks and the other small ones, maybe you should change the constrains a bit to improve it.