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First, that ODDR module on fp1_co is not needed.
Second, you should also use a PLL on FPGA2 if possible.
You need to set I/O constrains on the two FPGAs as normal.
In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock.
In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock.
The trick is that you need to keep the following relationship:
fp1_max_output_delay + fp2_max_input_delay = clock period
fp1_min_output_delay + fp2_min_input_delay = 0
This will be an iterative process.
I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed.
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Thank you for your reply.And I still have some questions to ask.
1、If I don't use the ODDR module on fp1_co,how do I let the output delay be as same as possible between fp1_co and fp1_do relative to clk1?
Or rather that it is unimportant.
2、Is it more better to use PLL on FPGA2?How does the FPGA shift the clock or the data to reach better timing?
3、for set_output_delay(max),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design?
4、for set_output_delay(min),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design?
5、for set_input_delay(max),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design?
6、for set_input_delay(min),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design?
7、How do you confirm whether your timing constraint is the best?by post_sim? or by other way?
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