How to do the timing constraint?

First, that ODDR module on fp1_co is not needed.

Second, you should also use a PLL on FPGA2 if possible.

You need to set I/O constrains on the two FPGAs as normal.

In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock.

In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock.

The trick is that you need to keep the following relationship:

fp1_max_output_delay + fp2_max_input_delay = clock period

fp1_min_output_delay + fp2_min_input_delay = 0

This will be an iterative process.

I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed.