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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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How to define timing constrains for input and output

If I look the timing analysis user guide, it recommend to use virtual clock to define timing constrain for input and output. But I don't know what's the difference between using virtual clock and clo...
XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thanks for your feedback. Could you look at my attached picture?

So there is no difference if I define adc_clock on FPGA port or just virtual clock, right?

I am just thinking virtual clock make you easy to analyze, but nothing different.

Please correct me if I am wrong.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

So this is a more complicated design. It's referred to as a data feedback design so there is no virtual clock here. The constraints you need are:

1) Input clock (base clock constraint with create_clock)

2) Generated clock output of PLL (use derive_pll_clocks)

3) Generated clock output of device (create_generated_clock with -source pointing to output clock pin of PLL and target pointing to get_ports [adc_clock})

4) False path on output clock path (so output clock path is not analyzed as a data path)

5) Input delay constraint (uses output generated clock in place of virtual clock; your constraint is close but needs to reference #3 above, not the output clock port)

  • XQSHEN's avatar
    XQSHEN
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Thanks a lot!