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Altera_Forum
Honored Contributor
Honored ContributorHow to Create a 2-Port RAM in MAX II LPM doen't support my feature Requirements
Dears
How to Create a 2-Port RAM by LPM of Altera , With Below Feature: RAM of 6bit Lenght, 8 words Depth Input Pins 1) Data[5..0] 2) Address[2..0] 3) AsyCLR OutPut Pins 1) DataOut[5..0] 2) Memory Full Output Pin( This pin Should Go HIGH when memory is FULL and LOW when it is Memory is CLEARed) PlsNote: No Clock is used Targeting device MAX II . How can we do with LPM ? If this is not possible with Altera LPM Can help me in Verilog or VHDL code with these feature. I am new to HDL's Regards, Satish2 Replies
Altera_ForumAlso, the Quartus II Handbook has a number of good RAM/ROM HDL examples. And the text editor has Edit -> Insert Template, with RAM/ROM examples there, too.
- Altera_Forum
Some quick issues to think about:
1) Having no clock doesn't make sense, as how would the hardware "know" when to write into the memory. If it's continuously writing, you'll have problems. For example, if your address changes from 000 to 111, not all bits will change at the same time. So it might pass thru addresses 100 and 101 on its way to 111. If those addresses get written with the value, you'll have problems. 2) If targeting the Max II family, there is no embedded memory and this will be created out of registers. As such, you can have synchronous writes and asynchronous reads. If targeting a family with embedded memory, it will have synchronous writes and reads. 3) Memory Full Output Pin? That makes sense with a FIFO, but not a RAM. A RAM is randomly accessed, meaning there is no definition of full. Is it full when you've written all 8 locations, or when you've written locations 0 and 7? You would need to write external logic to watch what has and has not been written to and make a decision based on your criteria. (Or use a FIFO, if that's what you really want.)
