How to connect an FPGA input port to QSYS pio inout port

Hi,

Sure, that is the way to do it if stripping of the inout functionality doesn't work.

But std_logic type is designed to be resolved. The problem might be that Altera (as a U.S. company) is putting all efforts to verilog, and supports vhdl only because they have to -with a minimum effort. I don't speak verilog, so don't know if there is similar functionality available.

At least the following code works in simulator (the behaviour of port 2) as intended. The synthesis tool has all the information needed to make the internal unidirectional (no tri-state buffers) netlist work with equivalent behaviour.

BR, -Topi

library ieee;
use ieee.std_logic_1164.all;
entity gpio is
	port(
		gio_inout: inout std_logic_vector(3 downto 1)
	);
end;
architecture test of gpio is
begin
	process
	begin
		gio_inout <= "000";
		wait for 1 ms;
		gio_inout <= "111";
		wait for 1 ms;
		gio_inout <= "ZZZ";
		wait for 1 ms;
	end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
	port(
		p1_inout: inout std_logic;
		p2_in: in std_logic;
		p3_out: out std_logic
	);
end;
architecture test of top is	   
	signal p2: std_logic;
begin
	gp: entity work.gpio
	port map(
		gio_inout(1) => p1_inout,
		gio_inout(2) => p2,
		gio_inout(3) => p3_out
	);
	
	p2 <= 'H' when to_01(p2_in) = '1' else 'L';
end;
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end;
architecture test of tb  is
	signal p1: std_logic;
	signal p2: std_logic;
	signal p3: std_logic;
begin
	t: entity work.top
	port map(
		p1_inout => p1,
		p2_in => p2,
		p3_out => p3
	);
	
	process
	begin		
		p1 <= '0';
		p2 <= '0';
		wait for 3 ms;
		p1 <= '1';
		p2 <= '1';
		wait for 3 ms;
		p1 <= 'Z';
		p2 <= 'Z';
		wait for 3 ms;
	end process;
end;