How to connect an FPGA input port to QSYS pio inout port

Hi,

I'm not an Altera guru, but I think what you're trying does not work in general.

The mode "inout" means that this signal connects to a pin through an input driver, and an output driver with tri-state control. Now you're connecting this inout to an input instead, through the net "helper". Now this means that there is a possibility that the FPGA pin is driven from the outside, which drives helper, but at the same time the PIO also wants to drive helper. This is forbidden.

Another way of looking at it: the inout of the entity implies that there is a way to drive the signal connected to it, but you cannot drive an input pin from that direction. The synthesis tool does not know how to handle this. The "multiple drivers" here refers to the tri-state-enable signal (an input has a permanently enabled tri-state-enable, but inout implies that the tri-state can be switched on and off).

The synthesis tool only seems to allow this when the top-level pin is also of mode inout. Of course, this could result in the FPGA driving a wire that is driven by another chip at the same time, but that's not the synthesis tool's concern. The synthesis tool expects all external drivers to be put into tri-state when the inout pin is driving.

Another thing you could to is to change the PIO to input-only mode. If you need bidirectional functionality on some, but not all pins of the PIO, you can do the following instead:

• create three PIOs, one of mode in, two of mode out

• the first PIO is your input

• the second is your output

• the third is the tri-state enable

• for each in-only pin, connect it to the corresponding pin of the first PIO, while leaving the corresponding pins of the other two PIOs open

• for each output-only pin, connect it to the corresponding pin of the second PIO, while leaving the corresponding pins of the other two PIOs open (actually, assignal a default value to the first PIO's input)

• for each inout-only pin, connect it to the corresponding pin of the first and second PIOs, while using the corresponding pin of the third PIO as a tri-state enable

The corresponding code in the top-level would look something like this:

fpga_pin: inout std_logic;
...
begin
...
pio_1_signal <= fpga_pin;
fpga_pin <= pio_2_signal when (pio_3_signal = '1') else 'Z';

(in fact, I believe that is exactly what the PIO does internally, as a inout PIO has three registers)

Best regards,

GooGooCluster