How to connect Altera's Clocked Video Output block to SDI II Tx block?

Hi

The following link shows the IOs of the SDI II Transmit IP core. It operates using single clock source 148.5MHz.

http://www.alterawiki.com/uploads/3/36/sdi_tx.png

I'm trying to figure out how to connect the Altera Clocked Video Output (CVO) to the SDI tx core. In my project, SDI II core is configured for SD/HD-SDI only (no 3G). And CVO is configured as 10bit with YCbCr format. Embedded sync is enabled.

Most of the signal connections are intuitive such as TRS, LN, etc. But what signal from the SDI core do I connect to the CVO's video clock input (i.e. to clock the video data out)? For HD-SDI, I believe it's supposed to be 74.25MHz. I'm wondering if I should generate that clock signal through PLL. Or should it be connected to "tx_dataout_valid"?

Thanks!