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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
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How to configure SDRAM for HPS ?

Hello, Is SDRAM configuration for a custom board should be done in Qsys ? I found the following which confused me if it should be done in qsys or not: https://forums.intel.com/s/question/0D50P0000...
  • sstrell's avatar
    sstrell
    6 years ago

    Timing constraints for most IP, including memory interfaces, are set up automatically when you generate the IP. You still need to provide constraints for clocks that drive your FPGA logic, but constraints for the IP itself are handled for you.

    Important side note: the tool is no longer called Qsys. It is now called Platform Designer. It still uses .qsys files, but you won't find the tool if you're looking for Qsys.

    #iwork4intel

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Timing constraints for most IP, including memory interfaces, are set up automatically when you generate the IP. You still need to provide constraints for clocks that drive your FPGA logic, but constraints for the IP itself are handled for you.

Important side note: the tool is no longer called Qsys. It is now called Platform Designer. It still uses .qsys files, but you won't find the tool if you're looking for Qsys.

#iwork4intel