Forum Discussion
rshal2
Occasional Contributor
Occasional ContributorHow to configure SDRAM for HPS ?
Hello, Is SDRAM configuration for a custom board should be done in Qsys ? I found the following which confused me if it should be done in qsys or not: https://forums.intel.com/s/question/0D50P0000...
Timing constraints for most IP, including memory interfaces, are set up automatically when you generate the IP. You still need to provide constraints for clocks that drive your FPGA logic, but constraints for the IP itself are handled for you.
Important side note: the tool is no longer called Qsys. It is now called Platform Designer. It still uses .qsys files, but you won't find the tool if you're looking for Qsys.
#iwork4intel
rshal2Occasional Contributor
Occasional ContributorThank you!
Is the right way to configure the timing should be by using ddr datasheet, or is it that the default parameters are in qsys should be sufficient ?
Thanks
