Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYes, and I do this all the time. If FPGA# 1 is configuring FPGA# 2, use four I/O pins from# 1 and connect them to dedicated JTAG pins of# 2. Then to program the FPGA# 2 directly, you can use the industry standard SVF file and Altera's Jrunner software to bit bang the I/O pins. In addition, if you want FPGA# 1 to program an EPCS flash, connect I/O pins from# 1 to Active Serial port of EPCS flash, and then you can use the RPD file and again Altera's Jrunner software to bit bang the active serial pins in FPGA# 1. Both the SVF and RPD file can be converted from SOF and POF using the Altera's conversion tool in Quartus II.
--- Quote Start --- through a JTAG... Is there any detailed timing diagrams ? Thanks in advance! --- Quote End ---