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lidongyang's avatar
lidongyang
Icon for New Contributor rankNew Contributor
2 years ago

how to config priority of EMIF on agilex 7 FPGA

Hi,

I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA

For example, I have 3 axi bridges connected to 1 EMIF. I want to set axi bridge 0 as the highest priority.

How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi?

Thanks

Configuration

4 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello lidongyang,


    Please find my feedback in the point below.


    "I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA"


    "How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi?"

    • Enable the option in EMIF IP -> Controller tab -> Efficiency -> Enable Command Priority Control.
    • Connect the ctrl_user_priority_hi to your user logic.
    • When this signal is high during read/write request, it will set the read/write request to high priority.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi lidongyang,


    Do you have any further questions in this thread?


    Regards,

    Adzim


    • lidongyang's avatar
      lidongyang
      Icon for New Contributor rankNew Contributor
      2 years ago

      please close the thread. Problem solved by myself

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.