how to config fpga with flash?

OK, that isn't conflicting with flash configuration anyhow. But you have the restriction that you can't capture signals directly at double data rate pins (DDIO registers) respectively with double data rate general. So you can't see the particular DDR timing, but you can see of course the sequences of control signals and addresses, and indirectly the RAM read and write data at the demultiplexed "slow" side of DDIO.