How to clock the module with different frequency?

Hi,

please, advise me what to do. I am working on DE3 with Stratix 3, and want the following module:

module DATA_Aq(Clk, In, ClkOut, Res);
input Clk, ClkOut;
input  In;
output reg Res;

to be clocked with different speed, for example, with 300, 350, 375, 400MHz. On DE3 board I have external source with 50MHz.

I generated 4 ALTPLL modules that performs 50MHz->300MHHz, 50MHz->350MHz, 50MHz->375MHz, 50MHz->400MHz and trying to do the following:

module DE3(OSC1_50, SW, InData, ClkOut, CLK_OUT)
//...
input OSC1_50; // input clock with 50Hz
input  SW; // depending on SW I wish to clock my project with 300, 350, 375, or 400MHz
input  InData;
input ClkOut;
output Res;
output CLK_OUT; // this is on board SMA connector where I need my 300-400MHz clock
//...
 wire Clk300, Clk350, Clk375, Clk400;
 wire Clk;
 DATA_Aq DATA_Aq_module(Clk, InData, ClkOut, Res);
 my_pll1 my_pll_module1(OSC1_50, Clk300);
 my_pll2 my_pll_module2(OSC1_50, Clk350);
 my_pll3 my_pll_module3(OSC1_50, Clk375);
 my_pll4 my_pll_module4(OSC1_50, Clk400);
// try to switch clocks depending on SW settings
 assign Clk=(SW)?((SW)?Clk400:Clk375):((SW)?Clk350:Clk300);
 assign CLK_OUT=(SW)?((SW)?Clk400:Clk375):((SW)?Clk350:Clk300);
endmodule

Additionally I should put the same clock to CLK_OUT pin of this board (it connects over SMA ouput of this board).

Actually my module does not work correctly: I am always getting the same Clk speed on Clk instead of 300,350,375,400MHz. Additionally, I cannot see FMax for Clk, however, I have .sdc file with

create_clock -name {Clk} -period 2.400 -waveform { 0.000 1.200 } 

Please, help me to understand what I did wrong?

Sincerely,

Ilghiz