How to calculate parameters for reconfigure a pll

I would offer You to open PLL core configuration window and check all the variables. I believe You'll find what You need.

Here's kinda obvious:

50MHz * 12 / 6 = 50MHz * 2 = 100MHz

50MHz * 10 / 4 = 50MHz * 2.5 = 125MHz

Hi,

Sorry to spam your thread, but i am having a similar problem. I understand where the 12 and 6 comes from, but how so i configure the modulus for M counter and N counter. The document only explains how to configure M/N counter values!

Thanks for help!

Pratish

Hi,

i have to reconfigure my pll on Cyclone IV. The PLL have an input frequency of 50MHz. I have some problem when i try to find the M,N,c0 value for low frequency (eg: 100KHz).

If i try to generate a PLL with this frequency from the Megawizard on quartus i obtain this values:M=12, N=1, c0=500. I note that there is also another section of parameters for c0 on the Megawizard page "Cascade TAP Settings (for c0)" with another post-scale counter and its value is 12. My question is: How i can set this post-scale counter through the ALTPLL_RECONFIG to obtain an output frequency of 100KHz ??

Thanks

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Hello,

i'm implementing a reconfigurable PLL using an ALTPLL e ALTPLLRECONFIG megafunction.

I initialize my PLL with an input freq of 50MHz and only c0 output clock with output freq of 100MHz.

I noticed in the Output clock tab this parameters:

MODULUS FOR M COUNTER = 12

MODULUS FOR N COUNTER = 1

POST SCALE COUNTER = 6

HIGH PERIOD COUNT = 3

LOW PERIOD COUNT = 3

MODE = even

now i changed the output freq from 100 to 125MHz

and the new parameters are

MODULUS FOR M COUNTER = 10

MODULUS FOR N COUNTER = 1

POST SCALE COUNTER = 4

HIGH PERIOD COUNT = 2

LOW PERIOD COUNT = 2

MODE = even

Now the question:

if i want to reconfigure my pll on-the-fly for generate an arbitrary frequency wich are the formulas to calculate the above parameters and pass them to the ALTPLLRECONFIG unit?

thanks for the help

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Hi,

Has anyone found any additional info for this? I am having the same problem and would like the formula to calculate M, N and Post Scale (C).

The documentation I found provides the following:

Fref = Fin/N

Fvco = Fin(M/N)

Fout = Fin(M/(N*C))

This info can be found here http://www.altera.com/support/devices/pll_clock/basics/pll-basics.html

I still do not understand how M,N and C are determined.

For example lets say my Fin = 25MHz and I want Fout = 37MHz.

The megawizard determines M=111, N=5 and C=15.

Does anyone know how these calculations were done?

With a constant Fin I would like to reconfigure my PLL to an arbitrary frequency.

Thank you

Was there any additional findings on this topic?

This page gives some of the formulas:

http://www.altera.com/support/devices/pll_clock/basics/pll-basics.html

FREF = FIN / N

FVCO = FREF × M = FIN × M/N

FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)

But I still do not understand how to calculate M, N and C for any given output frequency with a fixed input frequency.

Here's an example: With a fixed Fin=25MHz, I would like to generate Fout=37MHz. The Megawizard calculates M=111, N=5, C=15. How were these calculated?

I would like to reconfigure the PLL with an arbitrary Fout from 1MHz to 40MHz. I would use a processor to calculate these M,N and C values and then utilize the Altera PLL Reconfig Megafunction.

--- Quote Start ---

Was there any additional findings on this topic?

This page gives some of the formulas:

http://www.altera.com/support/devices/pll_clock/basics/pll-basics.html

FREF = FIN / N

FVCO = FREF × M = FIN × M/N

FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)

But I still do not understand how to calculate M, N and C for any given output frequency with a fixed input frequency.

Here's an example: With a fixed Fin=25MHz, I would like to generate Fout=37MHz. The Megawizard calculates M=111, N=5, C=15. How were these calculated?

I would like to reconfigure the PLL with an arbitrary Fout from 1MHz to 40MHz. I would use a processor to calculate these M,N and C values and then utilize the Altera PLL Reconfig Megafunction.

--- Quote End ---

As far i remember you can find different sets of M,N,C that can generate the same output frequency. As you can see from your example the M value is the greater number, than C and finally N. So you can write a very simple software (e.g. C#) with three FOR cycle one inside the other. The outer FOR is to increment N, the middle FOR is to increment C and the inner FOR is to increment M. At every iteration you must calculate the output frequency and check if the result is the desired frequency. If ok you have the set of M,N,C that generate your frequency. Please keep in mind that M,N,C are limited to 9bit wide (i think)

example:

for (n=1; n<n_max; n++)

for (c=1; c<c_max; c++)

for (m=1; m<m_max; m++)

calculate frequency and compare

exit if result is ok

I think that you can make something similar also in vhdl.

This is a late response but to help anyone else looking to do this. The above post will technically work. However, it may be very slow at getting the correct response and you are limited on how you constrain certain variables.

To combat this, I have used a Genetic Algorithm to calculate these values. The genetic optimization algorithm is used because it is able to handle both integer values and decimal values where as other algorithms can only handle decimal values. I run the algorithm in matlab because it is unbelievably easy and that is all I need at the moment, but I'm assuming that you can find a c or c++ implementation rather easily. You can do this by minimizing the error of the output frequency calculated from the equation from the actual output frequency you want. The equation for doing this looks like this below:

objF = ((Fin*(M+Mdec)/(N*C))-Fout)^2.

With your decision variables being M, Mdec, N, and C. From there, you can enter in constraints etc. Just google matlab genetic algorithm for documentation on how to use these algorithms.