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Honored Contributorhow to avoid this warning?
Recently,i am working with EPM570T10I,program with Verilog hdl.
When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew. Info: Detected ripple clock "flg_oc_1" as buffer But,the signal "flg_oc_1" is not a clock in my design ,it is just a pulse signal。 How should i do to avoid the warning? THX!!!11 Replies
Altera_Forum--- Quote Start --- Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew. Info: Detected ripple clock "flg_oc_1" as buffer But,the signal "flg_oc_1" is not a clock in my design ,it is just a pulse signal。 How should i do to avoid the warning? THX!!! --- Quote End --- Hi, if you really would to get rid of the warning you can use the assignment editor: Assignments -> Assignments Editor -> ( fill in node name in the "to" column) -> choose assignment "not a clock". Don't forget to set the Value to "on".
