Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

how to avoid this warning?

Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

If you really wwant to get rid of the warning you could use the output of the FF ( used as clock) as an enable signal of the other FF.

--- Quote End ---

For a more thorough discussion of using clock enables instead of ripple or gated clocks, see http://www.alteraforum.com/forum/showthread.php?t=2388.