KVane4
New Contributor
New ContributorHow to assign pin as a clock?
I have been using MAXII and MAXV CPLDs for some time, but have just started transferring to a MAX10 FPGA. I have started with some simple logic to generate clock signals and I get project compiles wi...
It sounds like you have not created a timing constraints file (.sdc) for the design. Once your clocks and I/O delays are constrained, you won't get those warnings anymore. To learn about SDC and creating timing constraints, start here:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
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