How to add a delay - Time digital converter (TDC) - begginer

Hello everyone,

I'm using a DE0 Nano SoC, and I have a PLL that provides me with a frequency of 500 MHz. I want to generate pulse bursts on my GPIO connector. So far, I can create pulses with a duration of 2n, and everything works very well. The issue is that with a frequency of 500 MHz, I can only shift my signal every 2 ns.

Therefore, I would like to implement a Time Digital Converter (TDC) to add a delay and be able to shift the signal by 250 ps and/or 500 ps and/or 1 ns. Actually, the precision of the timing doesn't matter much. What I want to understand is the methodology, how it's done.

I've seen in publications and elsewhere that there are two steps. The first is to create this delay chain, using code? A drawing in Quartus?

The second step is to manually place the "blocks" in chip planner. It seems to me that we can simply drag and drop these blocks, and the goal is to put them in series to control the delay. But how do we understand these blocks? They are quite complicated.

Also, from what I've seen elsewhere, our counterparts use carry4. Do we have an equivalent?

Figure 1 : what I want to do (is this correct?)

Figure 2 : Devil block