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Eric_truite's avatar
Eric_truite
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2 years ago

How to add a delay - Time digital converter (TDC) - begginer

Hello everyone, I'm using a DE0 Nano SoC, and I have a PLL that provides me with a frequency of 500 MHz. I want to generate pulse bursts on my GPIO connector. So far, I can create pulses with a dura...
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FvM's avatar
FvM
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2 years ago

Core clock is limited to 500 MHz, but you can generate higher resolution time shifts with phase shifted PLL clock, fixed or dynamically varied with delay step down to 125 ps (1/8 of PLL VCO period).

I have used it e.g. for high resolution PWM, time-equivalent sampling and soft CDR.

  • Eric_truite's avatar
    Eric_truite
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thank you for providing another method; I will go online to see what it entails. If you have more information, especially on how to accomplish this, for a PLL it's very simple, with 2 clicks Quartus does it for us. What about this implementation of the phase-shifted PLL clock? Nonetheless, I still want to understand how to make this TDC, for myself and for others in the future.