Contributor
Contributorhi,
I have already has this document on my hand and as I mentioned, I can access the flash successfully when I set the FPGA as the AS mode.
Now i need to access the flash when the FPGA was configured with PS mode. but it seems the GSFI IP can't work normally when the MSEL were set to PS mode.
For example, as below figure shows, when i tried to read the device ID on PS mode, it will be read as the "0xFFFFFFFF", but when i set the FPGA to AS, the device ID can be read out successfully.
So my question: how can my HPS access the flash(which is connected to FPGA dedicated pins, not general pins) when the FPGA was configured with PS mode?
thanks.
ContributorI also noticed some notes in the document as below:
Note: To access the AS configuration flash, set the MSEL pins of the FPGA devices to the AS configuration mode. To access the general purpose QSPI flash, enable the Disable Dedicated Active Serial Interface and Enable SPI Pins Interface parameter of this IP.
As I mentioned, our serial flash are connected to dedicated pins of CSS bank on Arria 10. you can refer to the red highlighted in below figure.
our board works on AS mode without issue, and we can access the serial flash to update the app image in system, this feature was realized.
In other scenario, we need the board work on PS mode. HPS boot first then configure the FPGA, and then we need to use the serial flash to store some user data.
But the serial flash is physically connected to the FPGA dedicated pins so I don't know if we can access it in PS mode.
