How to access the QSPI flash in PS mode?

hi,

I have already has this document on my hand and as I mentioned, I can access the flash successfully when I set the FPGA as the AS mode.

Now i need to access the flash when the FPGA was configured with PS mode. but it seems the GSFI IP can't work normally when the MSEL were set to PS mode.

For example, as below figure shows, when i tried to read the device ID on PS mode, it will be read as the "0xFFFFFFFF", but when i set the FPGA to AS, the device ID can be read out successfully.

So my question: how can my HPS access the flash(which is connected to FPGA dedicated pins, not general pins) when the FPGA was configured with PS mode?

thanks.

hi, Fakhrul

I just checked the link you provided, it is not for my scenario.

We have 2 QSPI flashes connected to A10.

the 1st one is connected to the HPS dedicated pins and is used for the HPS boot from QSPI. it contains the SPL/uboot image and the OS image and also our app.

the 2nd one is connected to the FPGA dedicated pins and is used for the FPGA AS mode configuration. it contains the FPGA image which we programmed into it via the *.JIC file.

so in this case the HPS boot from 1st QSPI and the FPGA configured from the 2nd QSPI seperaterly and both work well so far.

but in other situation, we need the 2nd QSPI to store some user data.

so we changed the booting mode. we also added the FPGA image file into the 1st QSPI flash. the HPS will boot firstly then configure the FPGA in PS mode during SPL/uboot stage and then the OS and app will boot. in this mode, both the HPS and FPGA images will only be stored in the 1st QSPI, the 2nd will be used as user data storage device.

but we found in this case we can't access the 2nd QSPI flash.

this is our question.

expect your prompt response.

thank you.

thanks for the reply.

please see my answer below.

• FPGA Retaining Control: Ensure the FPGA design releases the second QSPI after configuration in PS mode.(we can access the QSPI device successfully after FPGA AS configuration. for PS mode, the device doesn't work as a config device, so i don't think FPGA will still occupy this device. Or, can you tell me how to verify this?)
• Software Initialization: Verify that SPL/U-Boot initializes the second QSPI correctly for data storage and that the device tree or address mapping reflects the changes.(as i mentioned above, we can access the QSPI device successfully after FPGA AS configuration, we use the same SPL/U-boot when we try to access the device after PS configuration.)
• Pin and Clock Conflicts: Check for conflicts or misconfigurations in the QSPI pin assignments and clock settings.(since we can access the device after AS configuration, it can be verified that no pin or clock related error.)

thanks.