Forum Discussion
New ContributorHow long should rx_is_lockedtodata be asserted before a valid connection can ACTUALLY be assumed?
Hi,
If during the toggling, the rx_is_lockedtodata assertion duration is longer than 4us, you can try to workaround by monitoring the RX signal detect to ensure valid signal presence before you check on the CDR status. Note that you would need to enable 8b10b block to use RX signal detect. You will need to set the signal detect thresholds according to your specific setup. You may refer to the SATA/SAS recommended QSF assignments in the V series XCVR PHY IP user guide -> Cyclone V Transceiver Native PHY IP Core -> "Enable rx_std_signaldetect port" section for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Regular ContributorHi,
Sorry for the delay. Regarding your inquiry on the rx_clkout to rx_coreclkin, yes, you are right, you can drive the rx_coreclkin with other parallel clock with the same frequency and 0ppm with the rx_clkout. Based on my experience, generally this is used in bonding mode where we are using the master channel's rx_clkout to drive all the bonded channels' rx_coreclkin to reduce skew. For non-bonded channel, normally we will use the rx_clkout for a specific channel to drive its own rx_coreclkin. If you take a look at the figure "PCS Block Diagram of a Transceiver Channel in a Cyclone V Device" in CV device handbook, you would see a dedicated path for rx_clkout to be connected to the read of the FIFO. This path will be used if you connect rx_clkout to rx_corelkin at RTL.
Please let me know if there is any concern. Thank you.
