Forum Discussion
Sajith_K_Intel
New Contributor
New ContributorHow is an ALM used as Memory cell inside MLAB?
When an ALM inside MLAB is configured as a 32x2 simple dual-port memory, ALM block at least need 5-bit read address, 5-bit write address, write enable, clock, and byte enable. But for an ALUT, only ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
Upon checking, there is only a document about the Intel Stratix 10 LAB and MLAB Structure https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lab.pdf and Embedded Memory block types https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf but not detailing about the extra ports in the RAM.
Thanks.
Sajith_K_IntelThanks, I read this document already and there are no detailing about LUTRAM ports as you said.
I am not very sure who can answer this question.
