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Sajith_K_Intel's avatar
Sajith_K_Intel
Icon for New Contributor rankNew Contributor
6 years ago

How is an ALM used as Memory cell inside MLAB?

When an ALM inside MLAB is configured as a 32x2 simple dual-port memory, ALM block at least need 5-bit read address, 5-bit write address, write enable, clock, and byte enable. But for an ALUT, only ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I'm not sure of the exact answer to your question, but have you checked out any of the embedded memory user guides? This is the one for Stratix 10:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf

MLABs are made up of 10 ALMs so that's enough inputs for what is required for the whole MLAB. Where are you seeing that an individual ALM can be configured as a fully dual port 32x2 RAM with all those control signals?

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