Forum Discussion
Altera_Forum
Honored Contributor
13 years agoDuring the FPGA configuration phase, the FPGA configuration hardware will address and write the relevant data from the configuration bitstream into the RAM blocks.
There's no set/reset signal for the RAM blocks and there's no other storage of the RAM initial values within the FPGA. Even if you use the device wide reset (DEV_CLRn), it will only reset the flip-flops, it won't (can't) reset the RAM block contents.