Forum Discussion
Honored Contributorhow does quartus decide to remove logic?
I guess this is a bit of a newbie question (newbie to quartus not hardware design - I'm an old ASIC guy)...
I've crawled through the manual (well, it's 1200 pages long, so I'm sure I missed the discussion), but how does quartus decide to remove logic from a design? I have a big design (1.5M gates, 200K ff), and after mapping, 99% of the logic completely disappears and I am left with a few thousand luts. I found the redundant logic options, noprune (which I am trying now with assorted regs, but so far by putting noprune everywhere except in tasks and functions, I get a hard crash: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/database/netlist.cpp, Line: 4538 What's confusing especially is that I think I've been careful to make sure data flows in and out of this design.. It simulates by driving data in from outside the chip only (though there may be an initial block somewhere?) I presume that the problem is one of the follow: 1. map doesn't see clocks driven from registers (yes I read about clock generation), so it thinks all clocks a nailed to 0 or whatever... 2. map doesn't see that reset causes powerup fsms to start running.. 3. ??? registers coming up 0 puts everything in a strange state and quartus removes logic thinking it won't start running.. I guess any of the above are fine, but *there's no clue* I can find in the reports or in the quartus that tells me *why* it tossed out all 200,000+ registers ? I suspect that design assistant might, but I haven't quite figured that out either? Any hints much appreciated!11 Replies
Altera_ForumI wouldn't start randomly doing noprunes or anything like that. The analysis & synthesis messages state every cell removed and why, but it's not overly useful. If you have one register removed because you forgot to hook up its input(maybe a typo), and because it gets removed another 9,000 registers get removed because their input is tied off, then you have 9,001 messages about FFs removed. (That's a worst case scenario that they're all the same message, but you get the idea.) I believe the messages do occur in order though, so in this case the first one should be the one you care about and then 9,000 more. The problem is when you have a decent amount of logic that should get removed, as those messages may come before the stuff you're interested in.
The Analysis & Synthesis Report has section called something like Registers Removed Causing Further Reductions(or something similar, I can't remember). The purpose of this goal is to try and group them better for the reasons mentioned above. One other thing to try is to make a copy of your project, then right-click on a top-level hierarchy and Set as Top-level Entity(or go to Assignments -> Settings -> General and type the top-level in there) and just start synthesizing(no need to fit) sub-hierarchies and see what size they come in at. Probably start with reset logic or something like that, since I'm guessing that's the issue. (Heck, try disabling Power-Up Don't Care under Assginments -> Settings -> Analysis & Synthesis. I've only seen this help once, but it's possible.) My experience is the reduction is always a valid reason, just not something you expect. Good luck.
