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New ContributorHow do I transmit data at 1.434 Gbps in diff SSTL-12 in Cyclone 10 GX?
I hope to use a Cyclone 10 GX device to generate and transmit data at 1.434 Gbps (see my post https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593). The output logic standard is diff SSTL-12. I cannot use LVDS because its common mode voltage is incompatible with my receiver, which is an ASIC. Another post (https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593) states that the LVDS SERDES IP supports only LVDS. How can I transmit data at 1.434 in diff SSTL-12? Is there other SERDES IP that supports SSTL? Thanks.
5 Replies
TwincreeksHave anyone used Cyclone 10 GX general purpose IO pins to transmit data at 1.434 Gbps? Have any experts viewed my post? Could you please share the experience? Thanks.
AminT_IntelRegular Contributor
Hello,
The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.Thank you.- Twincreeks
Dear AminT_Intel,
Thank you for your reply. What is the highest data rate I can achieve with Cyclone 10 GX general purpose I/O pins in diff SSTL-12 standard and how can I achieve that data rate?
- AminT_Intel
Hello,
My previous answer will also be applied to this question. You can refer to these two documents for your design guidelines:
1. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdfThank you.
